The present invention relates generally to the field of high-speed signaling, and more particularly to timing signal generation within a delay-locked loop or phase-locked loop circuit.
Delay-locked loop (DLL) circuits are often used in high-speed signaling systems to generate signals for precisely timing sampling and transmission events within input/output circuits. FIG. 1 illustrates a prior-art delay-locked loop (DLL) circuit 100 that includes a reference loop 101, tracking loop 103 and clock generator 105. A complementary pair of reference clock signals, CLK and /CLK (102 and 104), are supplied to the reference loop 101 which, in turn, generates eight incrementally delayed clock signals 122, t0-t3 and /t0-/t3, referred to as phase vectors. Ideally the phase vectors are evenly phase-spaced within a time interval that corresponds to a cycle of the reference clock signal 102 such that a 45xc2x0 phase offset separates each phase-adjacent pair of phase vectors. The tracking loop 123 includes a mixer 117, clock tree circuit 119 and phase detector 115 which cooperate to generate a feedback clock signal 112 that is phase aligned with the reference clock signal 102. The mixer 117 receives the phase vectors 122 from the reference loop 101 and interpolates between a selected pair of the phase vectors to generate a mix clock signal 110. The mix clock signal 110 propagates through the clock tree circuit 119 (typically a set of amplifiers used to generate multiple instances of the mix clock signal 110) to generate the feedback clock signal 112. The phase detector 115 compares the feedback clock signal 112 with the reference clock signal 102 and generates a phase adjust signal 106 (U/D) according to which clock signal leads the other. For example, if the reference clock 102 signal leads the feedback clock signal 112, the phase detector 115 signals the mixer 117 (i.e., by appropriate state of the phase adjust signal) to shift interpolation toward the leading one of the selected phase vectors and away from the trailing phase vector, thereby advancing the phase of the feedback clock 112 and reducing the phase difference between the reference and feedback clock signals. If the reference clock signal 112 still leads (or lags) the feedback clock signal after interpolation has been shifted completely to one of the selected phase vectors, a different pair of phase vectors (i.e., bounding an adjacent phase range) is selected by the mixer 117. The DLL circuit 100 achieves phase lock when the phase of the feedback clock signal 112 becomes aligned with the phase of the reference clock signal 102.
The clock generator 105 includes a mixer 121 and clock tree circuit 123 that mirror the operation of the mixer 117 and clock tree circuit 119 within the tracking loop 103 to generate a local clock signal 116 (LCLK). The mixer 121 receives the phase adjust signal 106 generated within the mix loop 103 and therefore, when an offset control value 108 (OFFSET) is zero, performs nominally the same interpolation operation on the same pair of selected vectors as the mixer 117. Ideally, as the adjust signal 106 is incremented and decremented, the mixer 121 tracks the operation of the mixer 117 such that the local clock signal 116 and the feedback 112 are phase aligned. The offset control value 106 is summed with a count value maintained within the mixer 121 to provide a controlled, adjustable offset between the local clock signal 116 and reference clock signal 112, thereby allowing compensation for skew between the reference clock signal and a sampling instant, transmit instant or other event to be timed by the local clock signal 116.
FIG. 2 illustrates a prior-art phase mixer 121 in greater detail. The mixer 121 includes a counter 139, adder 141, bias voltage generator 143, and a bank of differential amplifiers 151. Each of the differential amplifiers 151 is formed by a pair of differentially coupled transistors having gate terminals coupled to receive a respective pair of complementary phase vectors, source terminals coupled to the drain terminal of a corresponding biasing transistor 153, and drain terminals coupled to a mix clock line 116 and complement mix clock line 118, respectively. The mix clock line 116 and complement mix clock lines are pulled up to a supply voltage via respective resistive elements, R. By this arrangement, when a given one of the biasing transistors 153 is biased to a current conducting state, the corresponding differential amplifier is enabled to draw current via resistive elements R in accordance with the input phase vectors, thereby causing the phase vector and its complement to appear on the complement mix clock line 118 and mix clock line 116 as a mix clock signal (MCLK) and complement mix clock signal (/MCLK), respectively. When two of the biasing transistors 153 are biased to a current conducting state, the input phase vectors supplied to the corresponding differential amplifiers are each enabled to contribute to the mix clock signal. The mix clock signal will initially slew (i.e., transition between states) at a rate determined by a leading one of the input phase vectors and then, after the trailing vector begins to transition, at a rate determined by the sum of the leading and trailing phase vectors, thereby yielding a mix clock signal phase that lies between the leading and trailing vectors according to the relative bias currents drawn by the biasing transistors 153.
The counter 171 is incremented and decremented in response to the phase adjust signal 106, and summed with the offset value 108 in adder circuit 141 to generate a phase control word 142. The phase control word 142 is decoded by decode logic 145 within the bias voltage generator 143 to generate a complementary pair of bias words 146 which are supplied to a digital-to-analog converter (DAC) 147. The most significant three bits of the complementary control values 146 indicate one of eight phase-adjacent pairs of phase vectors to be mixed to generate the mix clock signal, MCLK, and corresponding complementary phase vectors to be mixed to generate the complementary mix clock signal, /MCLK. Thus, the DAC 147 generates bias voltages on bias lines 154 in response to the complementary control values 146, such that at most two of the biasing transistors 153 are enabled at any given time, all other biasing transistors 153 being placed in a non-conducting state. As the count value is incremented by the counter, the bias voltage applied to one of the two enabled biasing transistors is increased, increasing the contribution of the corresponding phase vector to phase of the mix clock signal, and the bias voltage applied to the other selected biasing transistor is decreased, decreasing the contribution of the corresponding phase vector to the mix clock signal. Thus, as the count value is incremented and decremented, the phase of the mix clock signal is correspondingly advanced and delayed.
Because of the relatively small voltage steps generated by the DAC 147 and the high impedance load presented by the gates of biasing transistors 153, substantial time is typically required for each stepwise change in the output of DAC 147 to settle and produce a stable mix clock signal. Also, noise on the bias voltage lines 154 tends to produce phase jitter in the mix clock signals 116 and 118 so that capacitive elements are typically coupled to the bias voltage lines 154 as illustrated by (i.e., as illustrated by capacitive element, C, in FIG. 2). Unfortunately, capacitive loading of the bias voltage lines 154 further increases the time required for the lines 154 to settle in response to an increase or decrease of the bias voltage. Additionally, significant changes in the RC time constant result from process variations and from changes in temperature and voltage, making it difficult to quantify or predict the worst case settling time for the bias voltage lines 154. Consequently, several cycles of the reference clock signal are typically required for the phase of the output clock signal to stabilize in response to each bias voltage change. This is a significant disadvantage of the mixer 121, as a relatively long time is typically required to perform a phase locking operation in which numerous successive phase steps are needed to reach phase lock. The ability to rapidly switch between phase offsets in response to changes in the offset control value 108 is similarly limited by the DAC settling time.